1. Field of the Invention
The present invention relates to a semiconductor device having a multi-gate transistor and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the device in which the degradation due to negative bias temperature instability (NBTI) in triple gate transistors is reduced.
2. Description of Related Art
Multi-gate transistors, including triple gate and FinFET transistors, are one of the most promising candidates for 10 nm-level gate length MOSFETs. These transistors are based on fully-depleted silicon-on-insulator (SOI) MOSFETs that improve short channel characteristics and improve subthreshold behavior by offering an ideal subthreshold swing, which guarantees the scaling merits of speed enhancement and power reduction.
One reliability issue regarding scaled MOSFETs is negative bias temperature instability (NBTI). NBTI occurs in MOSFETs under constant voltage, where bias temperature stress under the constant voltage causes the generation of interface traps NIT between the gate oxide and silicon substrate, resulting in a threshold voltage VT shift and a loss of drive current ION as a function of time.
It is generally understood that NBTI degradation is due to hydrogenated silicon dangling bonds at the Si/SiO2 interface. NBTI-stress-induced interface trap generation has been identified as being due to breaking of Si—H bonds induced by inversion layer holes and subsequent diffusion of broken hydrogen in the form of H2 species.
Multi-gate transistors have different trap state densities at the interface for each channel due to different crystal orientations. This may also be due to the channels in the multi-gate transistors having oxides of different qualities. Therefore, an increase in trap states on the side channel surface of the multi-gate transistor may occur. In addition, the surrounding gate structure of a triple gate transistor locally enhances the electric field, which may also cause NBTI degradation. The NBTI effect is found to be more severe for PMOS FETs than NMOS FETs due to the presence of holes in the PMOS inversion layer that are known to interact with the oxide states. NBTI in p-MOSFETs, involving interface and bulk trap generation and causing device parameter degradation, is a serious reliability concern for both analog and digital CMOS circuits. NBTI is most problematic for high-performance or high-reliability devices, and analog/mixed-signal devices are more susceptible than digital devices.
FIG. 1A contains a schematic oblique view illustrating the structure of a conventional triple gate transistor. FIG. 1B contains a schematic cross-sectional view of the conventional triple gate transistor of FIG. 1A, taken along line I-I′ of FIG. 1A. The triple gate transistor of FIGS. 1A and 1B comprises an active region 10, a gate electrode 30, and a gate dielectric 40. The active region 10 has a top surface 12 and side surfaces 14. The top surface 12 of the active region has a crystal plane in a {100} orientation and the side surfaces 14 of the active region have crystal planes in a {110} orientation. It is generally understood that the crystal orientations {100} and {110} follow the Miller Indices convention, identifying a family of equivalent planes in a silicon diamond cubic lattice structure. In this configuration, NBTI occurs because there are a larger number of trap states in the {110} surfaces. The NBTI results in large threshold voltage shifts in the side channel transistors.
In addition, the interface traps can occur in the corners of the active region where the electric field in the gate oxide is stronger than the other flat gate oxide regions, and which can be another cause of NBTI in triple gate transistors.